Verilog——`include等预编译指令实例

Verilog与C语言包含头文件类似的预编译指令包括以下：

  • `define
  • `include
  • `ifdef
  • `elsif
  • `else
  • `endif

需要注意 `include指令后面对.vh文件的引用必须包含文件的 绝对路径！

  • 1）下面是使用预编译指令的一个实例。通过 ifdef ,elsif,`endif设置仿真和实际代码led0的翻转时间。
module top(
    input           clk50M      ,
    input           rst_n       ,
    output          led0
);
//localparam
//=========================================================
`define    TEST                             ;
`ifdef TEST                                 //仿真程序代码
    localparam TIME_1S      = 50_000        ;//1ms
    localparam TIME_500ms   = 25_000        ;//0.5ms
`elsif TRUE                                 //实际程序代码
    localparam TIME_1S      = 50_000_000    ;//1s
    localparam TIME_500ms   = 25_000_000    ;//0.5s
`endif

//=========================================================
reg [31:0]  num;


//=========================================================
//num
//---------------------------------------------------------
always @(posedge clk50M or negedge rst_n) begin
    if(~rst_n)
        num <= 32'd0;
    else if(num >= TIME_1S - 1)
        num <= 32'd0;
    else
        num <= num + 1'b1;
end
//led0
assign led0 = (num >= TIME_500ms) ? 1'b1 : 1'b0;
    
    
endmodule
  • 2）下面是使用预编译指令的另一个实例。
  1. head.vh文件代码
//head.vh

//`define  CAL_SUM
`define  CAL_MINUS
  1. cal.v文件代码
//cal.v

`include "D:\\study\\modelsim\\acd_3_9_4\\src\\head.vh"

module cal(
    input   [7:0]         ina         ,
    input   [7:0]         inb         ,
    output  [15:0]        out
);

`ifdef CAL_SUM
    assign out = ina + inb;
`elsif CAL_MINUS
    assign out = ina - inb;
`else
    assign out = ina * inb;
`endif

endmodule