verilog实现边沿检测
verilog边沿检测
下例是基于mealy状态机实现信号上升沿检测
module edge_detect
(
input wire clk,
input wire rst_n,
input wire level, //检测信号
output reg tick //输出信号
);
parameter zero = 1'b0,
one = 1'b1;
reg state_c, state_n;
always@(posedge clk or negedge rst_n)begin
if(!rst_n)
state_c <= zero;
else
state_c <= state_n;
end
always@(*)begin
tick = 1'b0;
state_n = state_c;
csae(state_c)
zero:
if(level)begin
tick = 1'b1;
state_n = one;
end
one:
if(~level)
state_n = zero;
default:
state_n = zero;
endcase
end
endmodule